Moore’s law: why power and heat limit faster chips

Whenever modern artificial intelligence systems train, they collide with power grids that struggle to keep pace. Shuttling information across warehouse server racks consumes two orders of magnitude more electricity than routing it within an individual package. At the same time, computing appetites for AI are climbing 50 times faster than historical hardware gains. It led former Intel leader Pat Gelsinger to warn that in our digital era, "energy capacity is economic capacity."

A listener wrote in asking how far Moore's law can truly push innovation, whether a smaller chip still matters, and what computing will look like in the decades ahead. We are mapping the journey from the physical ceilings stalling standard silicon to the engineering detours and radical architectures arriving over the next 50 years.

To see that barrier clearly, it helps to understand what Moore's law really was. When Gordon Moore published his piece in Electronics Magazine on April 19th, 1965, he was not announcing an inescapable law of physics like gravity. He was observing factory economics, noting that component complexity at minimum cost had doubled each year, a tempo he altered in 1975 to every 2 years. Transistor density—the volume of microscopic switches squeezed onto silicon at lowest cost—became a deliberate roadmap that aligned competition across the whole chip sector.

That benchmark sparked an astonishing transformation. Decades back, a supercomputer filled an entire room while pulling immense industrial power. Now, we carry a supercomputer in a pocket running on under 10 watts, with internal features nearing the size of individual silicon atoms. If modern packages already hold 100 billion switches at those atomic dimensions, why are chipmakers suddenly warning that the old game is over?

That alarm started two decades back, when the engine behind faster chips broke down. Until about 2004, chipmakers relied on Dennard scaling: smaller switches used less power, letting clock speeds rise without overheating. But rising leakage currents made dropping voltage impossible, pinning central processing units—a computer's primary calculating engines—against a heat ceiling of about 3.5 gigahertz.

Shrinking below 10 nanometers runs into quantum physics. When gates are only a few atoms thick, electrons leak directly through them in a process called quantum tunneling. Berkeley Lab scientists noted that Moore’s Law falters as switches approach atomic dimensions. As industry veteran Bob Patti puts it, atoms do not scale. To critics arguing the law has ended, this leakage proves that smaller switches deliver fading performance, bringing the diminishing returns of the shrink.

Even if switches shrink further, microscopic wiring creates interconnect delay, where wire resistance slows signals more than the switches do. Patti estimates wire accounts for roughly 95 percent of circuit delay and wasted power. Then comes the Von Neumann bottleneck, the physical divide separating processors from memory. Proponents of specialized architectures point out that in advanced artificial intelligence, ferrying data across that divide can burn more energy than the computation itself.

Behind the physics looms a financial barrier. Critics arguing the law is finished point out that designing a 2-nanometer chip can top 1 billion dollars, with fabrication tools doubling in cost every 4 years. Pat Gelsinger cautioned that confronting atomic limits makes shrinking prohibitively expensive. At TSMC, a spokesperson acknowledged to EE Times that “transistor scaling is indeed becoming more and more challenging, and costs are growing higher.” Gordon Moore himself sounded that warning in 2005: “The nature of exponentials is that you push them out and eventually disaster happens.”

Engineers are finding performance gains without shrinking switches. For decades, power lines and data wires shared the chip's crowded surface, creating severe bottlenecks. Backside power delivery untangles that congestion by moving electrical rails beneath the wafer. That leaves the front clear for data while letting power traces run thicker with less resistance. Intel prepared to roll this out at commercial scale with PowerVia alongside RibbonFET, its gate-all-around architecture that encases stacked nanosheets so circuits toggle faster in less space.

Engineers separated the risks before combining them. Ben Sell, Intel’s vice president of technology development, explained that running a test node allowed engineers to de-risk backside power before marrying it to fresh transistor architectures. On that experimental silicon, Intel reported the wiring change alone yielded a 6 percent boost in clock frequency and cut platform voltage droop by more than 30 percent, all without altering the switches.

The second major workaround is building upward. Producing one massive silicon slab is risky because a single microscopic defect scraps the entire die. Manufacturers sidestep that waste with modular chiplets—smaller dies bound together on one package. Intel deployed Foveros 3D packaging to combine compute, graphics, and neural tiles, a setup reportedly designed for energy-efficient on-device artificial intelligence. Backed by UCIe, an open standard linking dies across foundries, manufacturers are aiming to fit 1 trillion transistors into a package by 2030.

In university labs, researchers led by Qing Cao demonstrated monolithic 3D integration by stacking 3 transistor levels at heat no higher than 200 degrees Celsius, reporting yields from 98 to 100 percent. That matches what Julien Ryckaert, at the European semiconductor research hub imec, terms heterogeneous large-scale integration. As Ryckaert put it, “Moore’s Law only says I want more compute per dollar. There are other ways to accomplish that.” Packaging can buy us another decade of scaling, but does reshuffling silicon solve the crushing appetite of modern artificial intelligence?

Confronting the diminishing returns of the shrink, the industry is turning to domain-specific accelerators. These circuits are tailor-made for parallel math rather than general tasks, outperforming standard central processors by orders of magnitude on specialized workloads. As Nvidia head Jensen Huang put it, “performance without efficiency doesn’t scale,” arguing that “the breakthroughs don’t come from optimizing one piece. They come from redesigning the system.” Analysts at the semiconductor research group QNFO expect these dedicated accelerators will claim over 50 percent of data-center computing budgets by 2030.

That redesign targets that Von Neumann bottleneck from earlier, where ferrying data back and forth burns more power than calculating. As Rob Knoth at Cadence puts it, “the physics don’t care where your abstraction boundaries are,” leaving teams “moving from optimizing chips to optimizing systems.” To bypass that penalty, engineers turn to processing-in-memory. Executing computations directly inside memory arrays eliminates that costly data transfer, cutting off the heat at the source.

Brain-inspired neuromorphic computing takes another path, arranging circuits to mimic biological neurons and synapses to run neural networks on a tiny energy budget. Computing giant IBM demonstrated this on its NorthPole architecture, and Intel says its Loihi design handles neural tasks about 1,000 times more efficiently than standard computers. Nature already set the benchmark: the human brain carries out its vast parallel thinking on roughly 20 watts.

Still, engineers like Pat Gelsinger insist physical scaling is far from finished. He argues lithography remains the true bedrock of progress, backing light sources designed to work alongside machines from Dutch chip-equipment maker ASML to push beyond the usual 13.5-nanometer wavelength. In 2025, researchers demonstrated prototype chips integrating thousands of atomically thin 2D transistors to prevent leakage. But if electronics are running out of headroom, what happens when we look beyond silicon electrons entirely—to light and quantum states?

Over the next decade, chipmakers are turning to light. TSMC says its co-packaged optics technology is entering production, bringing fiber connections directly into the package so light replaces copper to eliminate wiring heat. Meanwhile, research funded by Intel alongside the National Science Foundation explores panel-scale integration up to 500 millimeters square, testing broad substrates linked by optical switches and low-loss waveguides.

Investor Thomas Andrae sees photonics offering a practical alternative for data centers until quantum machines mature. Yet optics brings trade-offs: optoelectronic devices lose about 30 percent of their energy simply converting electrons into photons and back. Quantum hardware faces hurdles too. Researcher Mrittunjoy Guha Majumdar cautions that fully autonomous quantum learning remains theoretical, calculating that benchmarking a 40-qubit setup takes over six hours for every single step.

Looking further ahead, government assessments conclude quantum computing could simulate molecular interactions for drug and material discovery beyond classical limits. Competing designs range from neutral atoms and trapped ions to superconducting systems like NOX, a 54-qubit computer in Bologna. Scaling advocates highlight PsiQuantum reaching 99.98 percent qubit preparation fidelity, while Japanese telecom operator NTT targets a one-million-qubit machine before the decade ends. Which approach achieves reliable fault tolerance remains an open question.

None of this points to a quantum laptop. Deloitte's Renata Jovanovic cautions that scaling and error correction remain steep barriers. As Nvidia's Jensen Huang observed, “Quantum computers won’t replace classical systems. They will work together,” noting elsewhere that “quantum needs enormous classical compute just to function.” Instead, reports project that real gains will rely on a hybrid computing stack—combining classical silicon with optical interconnects and quantum accelerators. When all these physical shifts, packaging tricks, and hybrid systems add up, what does the world look like for someone holding a device fifty years from now?

For everyday gadgets, this means smart sensors that monitor surroundings without draining batteries. A Dutch computing report notes that running artificial intelligence on wearables lets devices evaluate physiological signals locally, protecting privacy and lowering costs. Intel engineers propose monitors that learn someone’s typical pulse to flag abnormalities, while a patent outlines neuromorphic vision helping robots see in dim light. IBM researchers likewise expect brain-inspired chips to bring low-power intelligence to phones, drones, and vehicles.

At larger scale, reports project hybrid computing will speed discoveries across chemistry, climate, and medicine. Akira Shimada, head of Japanese telecom operator NTT, points to quantum systems balancing renewable power grids, designing energy-efficient materials, and accelerating drug discovery. Alongside them, a British government assessment finds optical and neuromorphic computing could make data centers sustainable enough to help meet net-zero targets.

Pat Gelsinger’s career traces this shift. Joining Intel at 18 as a technician, he became chief architect of the 80486 and eventually chief executive. After stepping down in December 2024, he held 100 meetings in 100 days before joining Playground Capital to back chip startups. That move answers his warning that energy capacity is economic capacity. His goal, he said, is to “make AI 10,000 times better, not 10 times,” on chips that “don’t look like today’s GPUs.”

That is how computing moves forward. Pure lithographic shrinking yields diminishing returns, shifting the industry toward heterogeneous integration—fusing silicon, memory, and specialized accelerators into unified systems. Analysts at QNFO forecast that the next two decades will bring this mixed convergence rather than a single silicon replacement. Decades ago, shrinking room-sized machines put a supercomputer in a pocket. Repeating that reduction over the next 30 years could fit an entire petaflop machine in that same pocket.

To keep following this shift, dig into Moore's Law and follow Intel. We have more stories covering it, so you'll be set whenever the chip industry turns next. Thanks for listening. Until next time.